module Arbiter(
  input clk,
  input rst,

  output msip_o,
  output msip_valid_o,
  input msip_i,
  output tim_int_req,

  input icache_direct,
  input icache_invalid,
  input icache_ren,
  input [63:0] icache_raddr,
  input [3:0] icache_rsize,
  output icache_rbusy,
  output [63:0] icache_rdata,
  output icache_rdata_valid,
  output icache_wbusy,
  input icache_wen,
  input [63:0] icache_waddr,
  input [63:0] icache_wdata,
  input [3:0] icache_wsize,
  
  input dcache_direct,
  input dcache_invalid,
  input dcache_ren,
  input [63:0] dcache_raddr,
  input [3:0] dcache_rsize,
  output dcache_rbusy,
  output [63:0] dcache_rdata,
  output dcache_rdata_valid,
  output dcache_wbusy,
  input dcache_wen,
  input [63:0] dcache_waddr,
  input [63:0] dcache_wdata,
  input [3:0] dcache_wsize

);

wire [63:0] SLAVE_AWADDR,MASTER_AWADDR_0,MASTER_AWADDR_1,MASTER_AWADDR_SEL_0,MASTER_AWADDR_SEL_1;
wire [2:0] SLAVE_AWPROT,MASTER_AWPROT_0,MASTER_AWPROT_1,MASTER_AWPROT_SEL_0,MASTER_AWPROT_SEL_1;
wire SLAVE_AWVALID,MASTER_AWVALID_0,MASTER_AWVALID_1,MASTER_AWVALID_SEL_0,MASTER_AWVALID_SEL_1;
wire SLAVE_AWREADY,MASTER_AWREADY_0,MASTER_AWREADY_1,MASTER_AWREADY_SEL_0,MASTER_AWREADY_SEL_1;
wire [63:0] SLAVE_WDATA,MASTER_WDATA_0,MASTER_WDATA_1,MASTER_WDATA_SEL_0,MASTER_WDATA_SEL_1;
wire [7:0] SLAVE_WSTRB,MASTER_WSTRB_0,MASTER_WSTRB_1,MASTER_WSTRB_SEL_0,MASTER_WSTRB_SEL_1;
wire SLAVE_WVALID,MASTER_WVALID_0,MASTER_WVALID_1,MASTER_WVALID_SEL_0,MASTER_WVALID_SEL_1;
wire SLAVE_WREADY,MASTER_WREADY_0,MASTER_WREADY_1,MASTER_WREADY_SEL_0,MASTER_WREADY_SEL_1;
wire [1:0] SLAVE_BRESP,MASTER_BRESP_0,MASTER_BRESP_1,MASTER_BRESP_SEL_0,MASTER_BRESP_SEL_1;
wire SLAVE_BVALID,MASTER_BVALID_0,MASTER_BVALID_1,MASTER_BVALID_SEL_0,MASTER_BVALID_SEL_1;
wire SLAVE_BREADY,MASTER_BREADY_0,MASTER_BREADY_1,MASTER_BREADY_SEL_0,MASTER_BREADY_SEL_1;
wire [63:0] SLAVE_ARADDR,MASTER_ARADDR_0,MASTER_ARADDR_1,MASTER_ARADDR_SEL_0,MASTER_ARADDR_SEL_1;
wire [2:0] SLAVE_ARPROT,MASTER_ARPROT_0,MASTER_ARPROT_1,MASTER_ARPROT_SEL_0,MASTER_ARPROT_SEL_1;
wire SLAVE_ARVALID,MASTER_ARVALID_0,MASTER_ARVALID_1,MASTER_ARVALID_SEL_0,MASTER_ARVALID_SEL_1;
wire SLAVE_ARREADY,MASTER_ARREADY_0,MASTER_ARREADY_1,MASTER_ARREADY_SEL_0,MASTER_ARREADY_SEL_1;
wire [63:0] SLAVE_RDATA,MASTER_RDATA_0,MASTER_RDATA_1,MASTER_RDATA_SEL_0,MASTER_RDATA_SEL_1;
wire [1:0] SLAVE_RRESP,MASTER_RRESP_0,MASTER_RRESP_1,MASTER_RRESP_SEL_0,MASTER_RRESP_SEL_1;
wire SLAVE_RVALID,MASTER_RVALID_0,MASTER_RVALID_1,MASTER_RVALID_SEL_0,MASTER_RVALID_SEL_1;
wire SLAVE_RREADY,MASTER_RREADY_0,MASTER_RREADY_1,MASTER_RREADY_SEL_0,MASTER_RREADY_SEL_1;

AXI_Lite_Arbiter inst_AXI_Lite_Arbiter
(
  .ACLK      (clk),
  .ARESETn   (~rst),
  .AWADDR_0  (MASTER_AWADDR_0),
  .AWPROT_0  (MASTER_AWPROT_0),
  .AWVALID_0 (MASTER_AWVALID_0),
  .WDATA_0   (MASTER_WDATA_0),
  .WSTRB_0   (MASTER_WSTRB_0),
  .WVALID_0  (MASTER_WVALID_0),
  .BREADY_0  (MASTER_BREADY_0),
  .ARADDR_0  (MASTER_ARADDR_0),
  .ARPROT_0  (MASTER_ARPROT_0),
  .ARVALID_0 (MASTER_ARVALID_0),
  .RREADY_0  (MASTER_RREADY_0),
  .AWREADY_0 (MASTER_AWREADY_0),
  .WREADY_0  (MASTER_WREADY_0),
  .BRESP_0   (MASTER_BRESP_0),
  .BVALID_0  (MASTER_BVALID_0),
  .ARREADY_0 (MASTER_ARREADY_0),
  .RDATA_0   (MASTER_RDATA_0),
  .RRESP_0   (MASTER_RRESP_0),
  .RVALID_0  (MASTER_RVALID_0),
  .AWADDR_1  (MASTER_AWADDR_1),
  .AWPROT_1  (MASTER_AWPROT_1),
  .AWVALID_1 (MASTER_AWVALID_1),
  .WDATA_1   (MASTER_WDATA_1),
  .WSTRB_1   (MASTER_WSTRB_1),
  .WVALID_1  (MASTER_WVALID_1),
  .BREADY_1  (MASTER_BREADY_1),
  .ARADDR_1  (MASTER_ARADDR_1),
  .ARPROT_1  (MASTER_ARPROT_1),
  .ARVALID_1 (MASTER_ARVALID_1),
  .RREADY_1  (MASTER_RREADY_1),
  .AWREADY_1 (MASTER_AWREADY_1),
  .WREADY_1  (MASTER_WREADY_1),
  .BRESP_1   (MASTER_BRESP_1),
  .BVALID_1  (MASTER_BVALID_1),
  .ARREADY_1 (MASTER_ARREADY_1),
  .RDATA_1   (MASTER_RDATA_1),
  .RRESP_1   (MASTER_RRESP_1),
  .RVALID_1  (MASTER_RVALID_1),
  .AWADDR    (SLAVE_AWADDR),
  .AWPROT    (SLAVE_AWPROT),
  .AWVALID   (SLAVE_AWVALID),
  .WDATA     (SLAVE_WDATA),
  .WSTRB     (SLAVE_WSTRB),
  .WVALID    (SLAVE_WVALID),
  .BREADY    (SLAVE_BREADY),
  .ARADDR    (SLAVE_ARADDR),
  .ARPROT    (SLAVE_ARPROT),
  .ARVALID   (SLAVE_ARVALID),
  .RREADY    (SLAVE_RREADY),
  .AWREADY   (SLAVE_AWREADY),
  .WREADY    (SLAVE_WREADY),
  .BRESP     (SLAVE_BRESP),
  .BVALID    (SLAVE_BVALID),
  .ARREADY   (SLAVE_ARREADY),
  .RDATA     (SLAVE_RDATA),
  .RRESP     (SLAVE_RRESP),
  .RVALID    (SLAVE_RVALID)
);


wire [5:0] io_sram0_addr;
wire io_sram0_cen;
wire io_sram0_wen;
wire [127:0] io_sram0_wmask;
wire [127:0] io_sram0_wdata;
wire [127:0] io_sram0_rdata;

wire [5:0] io_sram1_addr;
wire io_sram1_cen;
wire io_sram1_wen;
wire [127:0] io_sram1_wmask;
wire [127:0] io_sram1_wdata;
wire [127:0] io_sram1_rdata;

wire [5:0] io_sram2_addr;
wire io_sram2_cen;
wire io_sram2_wen;
wire [127:0] io_sram2_wmask;
wire [127:0] io_sram2_wdata;
wire [127:0] io_sram2_rdata;

wire [5:0] io_sram3_addr;
wire io_sram3_cen;
wire io_sram3_wen;
wire [127:0] io_sram3_wmask;
wire [127:0] io_sram3_wdata;
wire [127:0] io_sram3_rdata;

wire [5:0] io_sram4_addr;
wire io_sram4_cen;
wire io_sram4_wen;
wire [127:0] io_sram4_wmask;
wire [127:0] io_sram4_wdata;
wire [127:0] io_sram4_rdata;

wire [5:0] io_sram5_addr;
wire io_sram5_cen;
wire io_sram5_wen;
wire [127:0] io_sram5_wmask;
wire [127:0] io_sram5_wdata;
wire [127:0] io_sram5_rdata;

wire [5:0] io_sram6_addr;
wire io_sram6_cen;
wire io_sram6_wen;
wire [127:0] io_sram6_wmask;
wire [127:0] io_sram6_wdata;
wire [127:0] io_sram6_rdata;

wire [5:0] io_sram7_addr;
wire io_sram7_cen;
wire io_sram7_wen;
wire [127:0] io_sram7_wmask;
wire [127:0] io_sram7_wdata;
wire [127:0] io_sram7_rdata;
cache inst_icache
(
  .clk         (clk),
  .rst         (rst),
  .direct      (icache_direct),
  .invalid     (icache_invalid),
  .ren         (icache_ren),
  .raddr       (icache_raddr),
  .rsize       (icache_rsize),
  .rbusy       (icache_rbusy),
  .rdata       (icache_rdata),
  .rdata_valid (icache_rdata_valid),
  .wbusy       (icache_wbusy),
  .wen         (icache_wen),
  .waddr       (icache_waddr),
  .wdata       (icache_wdata),
  .wsize       (icache_wsize),
  .io_sram0_addr  (io_sram0_addr),
  .io_sram0_cen   (io_sram0_cen),
  .io_sram0_wen   (io_sram0_wen),
  .io_sram0_wmask (io_sram0_wmask),
  .io_sram0_wdata (io_sram0_wdata),
  .io_sram0_rdata (io_sram0_rdata),
  .io_sram1_addr  (io_sram1_addr),
  .io_sram1_cen   (io_sram1_cen),
  .io_sram1_wen   (io_sram1_wen),
  .io_sram1_wmask (io_sram1_wmask),
  .io_sram1_wdata (io_sram1_wdata),
  .io_sram1_rdata (io_sram1_rdata),
  .io_sram2_addr  (io_sram2_addr),
  .io_sram2_cen   (io_sram2_cen),
  .io_sram2_wen   (io_sram2_wen),
  .io_sram2_wmask (io_sram2_wmask),
  .io_sram2_wdata (io_sram2_wdata),
  .io_sram2_rdata (io_sram2_rdata),
  .io_sram3_addr  (io_sram3_addr),
  .io_sram3_cen   (io_sram3_cen),
  .io_sram3_wen   (io_sram3_wen),
  .io_sram3_wmask (io_sram3_wmask),
  .io_sram3_wdata (io_sram3_wdata),
  .io_sram3_rdata (io_sram3_rdata),
  .AWADDR      (MASTER_AWADDR_0),
  .AWPROT      (MASTER_AWPROT_0),
  .AWVALID     (MASTER_AWVALID_0),
  .AWREADY     (MASTER_AWREADY_0),
  .WDATA       (MASTER_WDATA_0),
  .WSTRB       (MASTER_WSTRB_0),
  .WVALID      (MASTER_WVALID_0),
  .WREADY      (MASTER_WREADY_0),
  .BRESP       (MASTER_BRESP_0),
  .BVALID      (MASTER_BVALID_0),
  .BREADY      (MASTER_BREADY_0),
  .ARADDR      (MASTER_ARADDR_0),
  .ARPROT      (MASTER_ARPROT_0),
  .ARVALID     (MASTER_ARVALID_0),
  .ARREADY     (MASTER_ARREADY_0),
  .RDATA       (MASTER_RDATA_0),
  .RRESP       (MASTER_RRESP_0),
  .RVALID      (MASTER_RVALID_0),
  .RREADY      (MASTER_RREADY_0)
);

cache inst_dcache
(
  .clk         (clk),
  .rst         (rst),
  .direct      (dcache_direct),
  .invalid     (dcache_invalid),
  .ren         (dcache_ren),
  .raddr       (dcache_raddr),
  .rsize       (dcache_rsize),
  .rbusy       (dcache_rbusy),
  .rdata       (dcache_rdata),
  .rdata_valid (dcache_rdata_valid),
  .wbusy       (dcache_wbusy),
  .wen         (dcache_wen),
  .waddr       (dcache_waddr),
  .wdata       (dcache_wdata),
  .wsize       (dcache_wsize),
  .io_sram0_addr  (io_sram4_addr),
  .io_sram0_cen   (io_sram4_cen),
  .io_sram0_wen   (io_sram4_wen),
  .io_sram0_wmask (io_sram4_wmask),
  .io_sram0_wdata (io_sram4_wdata),
  .io_sram0_rdata (io_sram4_rdata),
  .io_sram1_addr  (io_sram5_addr),
  .io_sram1_cen   (io_sram5_cen),
  .io_sram1_wen   (io_sram5_wen),
  .io_sram1_wmask (io_sram5_wmask),
  .io_sram1_wdata (io_sram5_wdata),
  .io_sram1_rdata (io_sram5_rdata),
  .io_sram2_addr  (io_sram6_addr),
  .io_sram2_cen   (io_sram6_cen),
  .io_sram2_wen   (io_sram6_wen),
  .io_sram2_wmask (io_sram6_wmask),
  .io_sram2_wdata (io_sram6_wdata),
  .io_sram2_rdata (io_sram6_rdata),
  .io_sram3_addr  (io_sram7_addr),
  .io_sram3_cen   (io_sram7_cen),
  .io_sram3_wen   (io_sram7_wen),
  .io_sram3_wmask (io_sram7_wmask),
  .io_sram3_wdata (io_sram7_wdata),
  .io_sram3_rdata (io_sram7_rdata),
  .AWADDR      (MASTER_AWADDR_1),
  .AWPROT      (MASTER_AWPROT_1),
  .AWVALID     (MASTER_AWVALID_1),
  .AWREADY     (MASTER_AWREADY_1),
  .WDATA       (MASTER_WDATA_1),
  .WSTRB       (MASTER_WSTRB_1),
  .WVALID      (MASTER_WVALID_1),
  .WREADY      (MASTER_WREADY_1),
  .BRESP       (MASTER_BRESP_1),
  .BVALID      (MASTER_BVALID_1),
  .BREADY      (MASTER_BREADY_1),
  .ARADDR      (MASTER_ARADDR_1),
  .ARPROT      (MASTER_ARPROT_1),
  .ARVALID     (MASTER_ARVALID_1),
  .ARREADY     (MASTER_ARREADY_1),
  .RDATA       (MASTER_RDATA_1),
  .RRESP       (MASTER_RRESP_1),
  .RVALID      (MASTER_RVALID_1),
  .RREADY      (MASTER_RREADY_1)
);
AXI_Lite_Sel inst_AXI_Lite_Sel
(
  .ACLK      (clk),
  .ARESETn   (~rst),
  .AWADDR    (SLAVE_AWADDR),
  .AWPROT    (SLAVE_AWPROT),
  .AWVALID   (SLAVE_AWVALID),
  .WDATA     (SLAVE_WDATA),
  .WSTRB     (SLAVE_WSTRB),
  .WVALID    (SLAVE_WVALID),
  .BREADY    (SLAVE_BREADY),
  .ARADDR    (SLAVE_ARADDR),
  .ARPROT    (SLAVE_ARPROT),
  .ARVALID   (SLAVE_ARVALID),
  .RREADY    (SLAVE_RREADY),
  .AWREADY   (SLAVE_AWREADY),
  .WREADY    (SLAVE_WREADY),
  .BRESP     (SLAVE_BRESP),
  .BVALID    (SLAVE_BVALID),
  .ARREADY   (SLAVE_ARREADY),
  .RDATA     (SLAVE_RDATA),
  .RRESP     (SLAVE_RRESP),
  .RVALID    (SLAVE_RVALID),
  .AWADDR_0  (MASTER_AWADDR_SEL_0),
  .AWPROT_0  (MASTER_AWPROT_SEL_0),
  .AWVALID_0 (MASTER_AWVALID_SEL_0),
  .WDATA_0   (MASTER_WDATA_SEL_0),
  .WSTRB_0   (MASTER_WSTRB_SEL_0),
  .WVALID_0  (MASTER_WVALID_SEL_0),
  .BREADY_0  (MASTER_BREADY_SEL_0),
  .ARADDR_0  (MASTER_ARADDR_SEL_0),
  .ARPROT_0  (MASTER_ARPROT_SEL_0),
  .ARVALID_0 (MASTER_ARVALID_SEL_0),
  .RREADY_0  (MASTER_RREADY_SEL_0),
  .AWREADY_0 (MASTER_AWREADY_SEL_0),
  .WREADY_0  (MASTER_WREADY_SEL_0),
  .BRESP_0   (MASTER_BRESP_SEL_0),
  .BVALID_0  (MASTER_BVALID_SEL_0),
  .ARREADY_0 (MASTER_ARREADY_SEL_0),
  .RDATA_0   (MASTER_RDATA_SEL_0),
  .RRESP_0   (MASTER_RRESP_SEL_0),
  .RVALID_0  (MASTER_RVALID_SEL_0),
  .AWADDR_1  (MASTER_AWADDR_SEL_1),
  .AWPROT_1  (MASTER_AWPROT_SEL_1),
  .AWVALID_1 (MASTER_AWVALID_SEL_1),
  .WDATA_1   (MASTER_WDATA_SEL_1),
  .WSTRB_1   (MASTER_WSTRB_SEL_1),
  .WVALID_1  (MASTER_WVALID_SEL_1),
  .BREADY_1  (MASTER_BREADY_SEL_1),
  .ARADDR_1  (MASTER_ARADDR_SEL_1),
  .ARPROT_1  (MASTER_ARPROT_SEL_1),
  .ARVALID_1 (MASTER_ARVALID_SEL_1),
  .RREADY_1  (MASTER_RREADY_SEL_1),
  .AWREADY_1 (MASTER_AWREADY_SEL_1),
  .WREADY_1  (MASTER_WREADY_SEL_1),
  .BRESP_1   (MASTER_BRESP_SEL_1),
  .BVALID_1  (MASTER_BVALID_SEL_1),
  .ARREADY_1 (MASTER_ARREADY_SEL_1),
  .RDATA_1   (MASTER_RDATA_SEL_1),
  .RRESP_1   (MASTER_RRESP_SEL_1),
  .RVALID_1  (MASTER_RVALID_SEL_1)
);

axi_mem inst_axi_mem
(
  .ACLK    (clk),
  .ARESETn (~rst),
  .AWADDR  (MASTER_AWADDR_SEL_0),
  .AWPROT  (MASTER_AWPROT_SEL_0),
  .AWVALID (MASTER_AWVALID_SEL_0),
  .AWREADY (MASTER_AWREADY_SEL_0),
  .WDATA   (MASTER_WDATA_SEL_0),
  .WSTRB   (MASTER_WSTRB_SEL_0),
  .WVALID  (MASTER_WVALID_SEL_0),
  .WREADY  (MASTER_WREADY_SEL_0),
  .BRESP   (MASTER_BRESP_SEL_0),
  .BVALID  (MASTER_BVALID_SEL_0),
  .BREADY  (MASTER_BREADY_SEL_0),
  .ARADDR  (MASTER_ARADDR_SEL_0),
  .ARPROT  (MASTER_ARPROT_SEL_0),
  .ARVALID (MASTER_ARVALID_SEL_0),
  .ARREADY (MASTER_ARREADY_SEL_0),
  .RDATA   (MASTER_RDATA_SEL_0),
  .RRESP   (MASTER_RRESP_SEL_0),
  .RVALID  (MASTER_RVALID_SEL_0),
  .RREADY  (MASTER_RREADY_SEL_0)
);

CoreLocalInterrupt inst_CoreLocalInterrupt
(
  .ACLK    (clk),
  .ARESETn (~rst),
  .AWADDR  (MASTER_AWADDR_SEL_1),
  .AWPROT  (MASTER_AWPROT_SEL_1),
  .AWVALID (MASTER_AWVALID_SEL_1),
  .AWREADY (MASTER_AWREADY_SEL_1),
  .WDATA   (MASTER_WDATA_SEL_1),
  .WSTRB   (MASTER_WSTRB_SEL_1),
  .WVALID  (MASTER_WVALID_SEL_1),
  .WREADY  (MASTER_WREADY_SEL_1),
  .BRESP   (MASTER_BRESP_SEL_1),
  .BVALID  (MASTER_BVALID_SEL_1),
  .BREADY  (MASTER_BREADY_SEL_1),
  .ARADDR  (MASTER_ARADDR_SEL_1),
  .ARPROT  (MASTER_ARPROT_SEL_1),
  .ARVALID (MASTER_ARVALID_SEL_1),
  .ARREADY (MASTER_ARREADY_SEL_1),
  .RDATA   (MASTER_RDATA_SEL_1),
  .RRESP   (MASTER_RRESP_SEL_1),
  .RVALID  (MASTER_RVALID_SEL_1),
  .RREADY  (MASTER_RREADY_SEL_1),
  .tim_int_req(tim_int_req),
  .msip_i(msip_i),
  .msip_o(msip_o),
  .msip_valid_o(msip_valid_o)
);

S011HD1P_X32Y2D128_BW isnt_sram0(
  .Q(io_sram0_rdata),
  .CLK(clk),
  .CEN(io_sram0_cen),
  .WEN(io_sram0_wen),
  .BWEN(io_sram0_wmask),
  .A(io_sram0_addr),
  .D(io_sram0_wdata)
);
S011HD1P_X32Y2D128_BW isnt_sram1(
  .Q(io_sram1_rdata),
  .CLK(clk),
  .CEN(io_sram1_cen),
  .WEN(io_sram1_wen),
  .BWEN(io_sram1_wmask),
  .A(io_sram1_addr),
  .D(io_sram1_wdata)
);
S011HD1P_X32Y2D128_BW isnt_sram2(
  .Q(io_sram2_rdata),
  .CLK(clk),
  .CEN(io_sram2_cen),
  .WEN(io_sram2_wen),
  .BWEN(io_sram2_wmask),
  .A(io_sram2_addr),
  .D(io_sram2_wdata)
);
S011HD1P_X32Y2D128_BW isnt_sram3(
  .Q(io_sram3_rdata),
  .CLK(clk),
  .CEN(io_sram3_cen),
  .WEN(io_sram3_wen),
  .BWEN(io_sram3_wmask),
  .A(io_sram3_addr),
  .D(io_sram3_wdata)
);
S011HD1P_X32Y2D128_BW isnt_sram4(
  .Q(io_sram4_rdata),
  .CLK(clk),
  .CEN(io_sram4_cen),
  .WEN(io_sram4_wen),
  .BWEN(io_sram4_wmask),
  .A(io_sram4_addr),
  .D(io_sram4_wdata)
);
S011HD1P_X32Y2D128_BW isnt_sram5(
  .Q(io_sram5_rdata),
  .CLK(clk),
  .CEN(io_sram5_cen),
  .WEN(io_sram5_wen),
  .BWEN(io_sram5_wmask),
  .A(io_sram5_addr),
  .D(io_sram5_wdata)
);
S011HD1P_X32Y2D128_BW isnt_sram6(
  .Q(io_sram6_rdata),
  .CLK(clk),
  .CEN(io_sram6_cen),
  .WEN(io_sram6_wen),
  .BWEN(io_sram6_wmask),
  .A(io_sram6_addr),
  .D(io_sram6_wdata)
);
S011HD1P_X32Y2D128_BW isnt_sram7(
  .Q(io_sram7_rdata),
  .CLK(clk),
  .CEN(io_sram7_cen),
  .WEN(io_sram7_wen),
  .BWEN(io_sram7_wmask),
  .A(io_sram7_addr),
  .D(io_sram7_wdata)
);
endmodule
